1. Field
Example embodiments relate to a voltage generation circuit and/or a method thereof, and for example, to a voltage generation circuit generating a voltage smaller than a power source voltage in potential and/or a method of generating a voltage smaller than a power source voltage in potential.
2. Description of Related Art
FIG. 4 shows a conventional static-voltage generation circuit configured to generate a static voltage in a semiconductor memory device. Referring to FIG. 4, first and second reference potentials VREF1 and VREF2 link with inverted input nodes of first and second operational amplifiers 30 and 31, respectively. Non-inverted input nodes of the operational amplifiers 30 and 31 are coupled to a central tap P of a resistor 34 in common. A source of a PMOS transistor 32 is connected to a power source voltage VCC and a gate of the PMOS transistor 32 is coupled to an output node of the first operational amplifier 30. A drain of an NMOS transistor 33 is connected to a drain of the PMOS transistor 32 and a gate of the NMOS transistor 33 is coupled to an output node of the second operational amplifier 31. A source of the NMOS transistor 33 is connected to a ground. The resistor 34 is connected between the drain of the NMOS transistor 33 and the ground. An output terminal 35 is connected to the drain of the NMOS transistor 33.
The first and second operational amplifiers 30 and 31 compare a voltage, which is divided from a voltage of the output terminal 35 by the central tap P of the resistor 34, with the first and second reference voltage potentials VREF1 and VREF2, respectively. According to a result of the comparison, the PMOS and NMOS transistors 32 and 33 are controlled to generate a required voltage at the output terminal 35. In generating the required voltage at the output terminal 35 lower than the power source voltage, a smaller gap between the power source voltage and an output voltage, e.g., the required voltage at the output terminal 35, causes a larger difference between operation ranges, for example a rising up and falling down, of the output voltage. Because of the larger difference between operation ranges of the output voltage, a valance of amplification rates may vary more widely, more easily causing instability in a level of the output voltage. As a result, it is more difficult to stabilize an output voltage level in a shorter time.
However, another conventional reference voltage generation circuit is configured to generate a reference voltage lower than a power source voltage. In another conventional reference voltage generation circuit, an N-channel depletion transistor M3 having a gate and source which are saturation-connected with each other for generating first constant currents is employed. However, in a semiconductor memory device, current characteristics of MOS transistors are more easily affected from disproportion of fabrication processes and temperature variation.